This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-066954, filed Mar. 10, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
This present invention relates to a semiconductor memory device which is reprogrammable, and particularly relates to a reprogrammable semiconductor memory device having a page latch.
2. Related Art
In some of a nonvolatile semiconductor memory device (EEPROM) which is reprogrammable by one byte to by a few tens bytes (for one page), one latch circuit (page latch circuit) for retaining one page data is provided for every bit line. In this specification, the nonvolatile semiconductor memory device is called a semiconductor memory device having a page latch.
An operation of a conventional nonvolatile semiconductor memory device having a page latch will be explained. FIGS. 18a to 18c indicate data flow diagrams at a data loading operation, at a programming operation and at a read operation in a conventional semiconductor memory device having a page latch, respectively. First of all, as shown in FIG. 18a, one-page program data are loaded to a page latch. When one-page program data are stored in the page latch, typically one page data stored in memory cells are erased.
As shown in FIG. 18b, the one-page program data in the page latch are simultaneously written to the one-page memory cells, whose previous data have been erased. Also, when a data in the memory cell is read out, as shown in FIG. 18c, a selected memory cell is connected to a read out circuit and the data is read from the selected memory cell.
However, once a data loading operation is started, the operation continues to a data erasing operation and a data programming operation automatically in the conventional nonvolatile semiconductor memory device with a page lath. Also, in the data reading out operation, the conventional nonvolatile semiconductor memory device only has a mode in which the operation reads out data programmed to the memory cell.
In such conventional nonvolatile memory devices with page latches, when a data is programmed to a memory cell and the programmed data is read out from the memory cell, and assuming that the data which is read out includes an error, it is very hard to determine whether the data which is programmed to the memory cell has included the error or the data which is read out from the memory cell was broken at the read out circuit.
Also, when you test the page latch and the read out circuit in the conventional nonvolatile semiconductor memory device, you need a very long time to test because a data is programmed to a memory cell automatically.
An object of this invention is to provide a semiconductor memory device capable of making it easy to determine a cause of an error if there is an error in reprogrammed data and carrying out a test of the page latches and the read out circuits in a short time.
In order to accomplish the above object of this invention, a semiconductor memory device related to this invention comprises a bit line to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read out circuit connected to the data bus and a data transfer circuit group has an ability to directly transfer the data latched in the latch circuit, to the read out circuit without via the memory cell.
The data transfer circuit may have a first operation mode to transfer a data loaded to the latch circuit, to the memory cell connected to the bit line, a second operation mode to a data read out from the memory cell to the read circuit and a third operation mode to directly transfer the data latched in the latch circuit, to the read circuit.
The third operation mode may be performed during a test of the semiconductor memory device.
The first and the second operation mode may be performed during a normal operation and the third operation mode is performed during a test of the semiconductor memory device.
The data transfer circuit group may have a first transfer gate, an one end of which electrically connected to the bit line, a second transfer gate, an one end of which electrically connected to an other end of the first transfer gate, a third transfer gate, an one end of which electrically connected to the one end of the first transfer gate and an other end of which electrically connected to the latch circuit and a fourth transfer gate, an one end of which electrically connected to an other end of the second transfer gate and an other end of which electrically connected to the read out circuit.
It is desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is directly transferred to the read out circuit without via the memory cell, the first transfer gate is set to OFF state, the second transfer gate is set to ON state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state.
A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.
It may be desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to OFF state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gate are set to ON state, the memory cell is set to non-selected state.
A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.
The semiconductor memory device having a data latch circuit further comprises a control circuit controlling the transfer gate group so as to achieve a first and second operation modes, the first operation mode programming a data loaded to the latch circuit, to the memory cell, the second operation mode stopping an operation after a data is loaded to the latch circuit.
The first operation mode may be performed at a normal operation, the second operation mode is performed at a testing operation.
The semiconductor memory device having a data latch circuit further comprises an error correction circuit is electrically connected to the read out circuit.
A semiconductor memory device having a data latch circuit comprise, a bit line to which a reprogrammable memory cell is connected, a data bus on which data is transferred, a latch circuit having latching the data transferred on the data bus, a read out circuit connected to the data bus and a data transfer circuit group, wherein the data transfer circuit group is controlled so as to transfer the data latched in the latch circuit, to the read out circuit without via the memory cell.
The data transfer circuit may have a first operation mode to transfer a data loaded to the latch circuit, to the memory cell connected to the bit line, a second operation mode to a data read out from the memory cell to the read circuit and a third operation mode to directly transfer the data latched in the latch circuit, to the read circuit.
The third operation mode may be performed during a test of the semiconductor memory device.
The first and the second operation mode may be performed during a normal operation and the third operation mode may be performed during a test of the semiconductor memory device.
It is desirable that the data transfer circuit group has a first transfer gate, an one end of which electrically connected to the bit line, a second transfer gate, an one end of which electrically connected to an other end of the first transfer gate, a third transfer gate, an one end of which electrically connected to the one end of the first transfer gate and an other end of which electrically connected to the latch circuit and a fourth transfer gate, an one end of which electrically connected to an other end of the second transfer gate and an other end of which electrically connected to the read out circuit.
It is desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is directly transferred to the read out circuit without via the memory cell, the first transfer gate is set to OFF state, the second transfer gate is set to ON state, the third transfer gate is set to ON state, the fourth transfer gate is set to ON state.
A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.
It may be desirable that when a data loaded to the latch circuit is transferred to the memory cell, the first transfer gate is set to ON state, the second transfer gate is set to OFF state, the third transfer gate is set to ON state, the fourth transfer gate is set to OFF state, when a data read out from the memory cell is transferred to the read out circuit, the first transfer gate is set to ON state, the second transfer gate is set to ON state, the third transfer gate is set to OFF state, the fourth transfer gate is set to ON state, when a data loaded to the latch circuit is transferred to the read out circuit, the first to the fourth transfer gate are set to ON state, the memory cell is set to non-selected state.
A voltage of a gate electrode of the third transfer gate may be gradually raised to set to ON state.
The semiconductor memory device having a data latch circuit further comprises a control circuit controlling the transfer gate group so as to achieve a first and second operation modes, the first operation mode programming a data loaded to the latch circuit, to the memory cell, the second operation mode stopping an operation after a data is loaded to the latch circuit.
The first operation mode may be performed at a normal operation, the second operation mode is performed at a testing operation.
The semiconductor memory device having a data latch circuit further comprises an error correction circuit is electrically connected to the read out circuit.
A test method of a semiconductor memory device comprises steps of; latching data at a page latch via a data bus on which the data are transferred, transferring the data latched in the page latch to a cell matrix for stored the data at a first mode and to a read out circuit at a second mode for testing whether or not an error occurs at a data transfer circuit group including the data bus, the page latch and read out circuit.